1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a structure thereof, and more particularly to a method of manufacturing a solid-state image sensor and a structure thereof.
2. Description of the Background Art
FIG. 6 is a circuit diagram showing the structure of a pixel of a conventional CMOS image sensor (cf. S. Inoue et al., xe2x80x9cA 3.25 M-pixel APS-C size CMOS Image Sensorxe2x80x9d, ITE Technical Report, Vol.25, No.28, pp.37-41). As shown in FIG. 6, a pixel of the CMOS image sensor includes a photodiode 101, a transfer MOS transistor 102 for transferring all of electrons generated in the photodiode 101 to a node FD, a reset MOS transistor 103 for resetting the potentials of the photodiode 101 and the node FD, a source follower MOS transistor 104 for amplifying the potential of the node FD and a select MOS transistor 105 for selecting a line to be read out.
The photodiode 101 has its cathode connected to the source of the transfer MOS transistor 102. The transfer MOS transistor 102 has its drain connected to both the source of the reset MOS transistor 103 and the gate of the source follower MOS transistor 104 through the node FD. The reset MOS transistor 103 has its drain connected to a power supply for supplying a predetermined power supply potential VDD.
An operation of the conventional CMOS image sensor will be described now. First, gate voltages Vt and Vres are applied to turn on the transfer MOS transistor 102 and the reset MOS transistor 103, allowing the potentials of the photodiode 101 and the node FD to be reset at the power supply potential VDD. Upon completion of the reset, the application of the gate voltage Vres is stopped to turn off the reset MOS transistor 103.
Next, all of electrons generated by photoelectric conversion of incident light in the photodiode 101 are transferred to the node FD by the transfer MOS transistor 102. The potential of the node FD varies in accordance with the amount of electrons as transferred. Next, a gate voltage Vsel is applied to turn on the select MOS transistor 105. The potential of the node FD as varied is amplified by the source follower MOS transistor 104 to be input to a post-stage readout circuit.
FIG. 7 is a cross-sectional view showing part of the structure of the conventional CMOS image sensor in which the photodiode 101 and the transfer MOS transistor 102 are formed, although illustration of an interlayer insulation film and metallic interconnection is omitted. A P well 111 is formed in an upper surface of the N-type semiconductor substrate 110. An element isolating insulation film 112 is formed on an upper surface of the P well 111. In an element forming region defined by the element isolating insulation film 112, a gate structure 115 having a gate insulation film 113 and a gate electrode 114 laminated in this order is formed on the upper surface of the P well 111.
In the element forming region, a P+-type impurity-introduced region 116, an N-type impurity-introduced region 117 and an N+-type impurity-introduced region 119 are formed in the upper surface of the P well 111. The N-type impurity-introduced region 117 is formed deeper than the P+-type impurity-introduced region 116. The N-type impurity-introduced region 117 and the P+-type impurity-introduced region 116 constitute a photodiode 118, which corresponds to the photodiode 101 shown in FIG. 6. Specifically, the anode and cathode of the photodiode 101 shown in FIG. 6 correspond to the P+-type impurity-introduced region 116 and the N-type impurity-introduced region 117 shown in FIG. 7, respectively.
Part of the N-type impurity-introduced region 117 (i.e., an end portion on the side of the N+-type impurity-introduced region 119) extends under the gate structure 115. The N+-type impurity-introduced region 119 is opposite to the N-type impurity-introduced region 117 with a channel-forming region under the gate structure 115 interposed therebetween. The gate structure 115, the N-type impurity-introduced region 117 and the N+-type impurity-introduced region 119 constitute an MOS transistor (hereinafter referred to as xe2x80x9cMOS transistor Xxe2x80x9d), which corresponds to the transfer MOS transistor 102 shown in FIG. 6. Specifically, the gate, source and drain of the transfer MOS transistor 102 shown in FIG. 6 correspond to the gate electrode 114, the N-type impurity-introduced region 117 and the N+-type impurity-introduced region 119 shown in FIG. 7, respectively. The N+-type impurity-introduced region 119 also corresponds to the node FD shown in FIG. 6.
FIG. 8 is a cross-sectional view showing an example of a step of forming the N-type impurity-introduced region 117. The gate structure 115 has already been formed on the upper surface of the P well 111. Although not shown in FIG. 8, a resist pattern is also formed which has an opening over a region where the N-type impurity-introduced region 117 is to be formed. As described above, part of the N-type impurity-introduced region 117 needs to be formed extending under the gate structure 115. Thus, when forming the N-type impurity-introduced region 117, ion implantation of N-type impurities 120 is performed obliquely with respect to the upper surface of the P well 111 while rotating a wafer. The N-type impurities 120 are therefore implanted also under the end portion of the gate structure 115. Such ion implantation performed obliquely while rotating a wafer is hereinafter referred to as xe2x80x9coblique-rotating implantationxe2x80x9d in the present specification.
FIG. 9 is a cross-sectional view showing another example of a step of forming the N-type impurity-introduced region 117. First, N-type impurities are ion-implanted into the P well 111 from the vertical direction with respect to the upper surface of the P well 111 using the gate structure 115 and the aforementioned resist pattern as an implantation mask, thereby forming an N-type impurity-implanted region 122. Such ion implantation performed vertically is hereinafter referred to as xe2x80x9cvertical implantationxe2x80x9d in the present specification. Next, heat treatment is performed excessively as compared to a normal annealing which activates impurities after ion implantation, resulting in excessive thermal diffusion of the N-type impurities in the N-type impurity-implanted region 122. This causes the N-type impurity-implanted region 122 to extend outwardly and isotropically, so that the consequently obtained N-type impurity-introduced region 117 partly extends under the end portion of the gate structure 115.
The above-described method of manufacturing the conventional semiconductor device has the following disadvantages in the step of forming the N-type impurity-introduced region 117.
As shown in FIG. 8, the gate electrode 114 actually has a tapered shape. In oblique implantation, the concentration distribution of the N-type impurity-introduced region 117 in the P well 111 varies in accordance with angle A of the taper.
Further, in forming the resist pattern, RCA cleaning may previously be performed in many cases for promoting resist adhesion. A wet process performed at that time may cause an end portion 121 of the gate insulation film 113 to be removed. The concentration distribution of the N-type impurity-introduced region 117 in the P well 111 also varies in accordance with the degree of removal of the end portion 121 of the gate insulation film 113.
Such variations in the concentration distribution of the N-type impurity-introduced region 117 in the P well 111 not only cause variations in properties of the photodiode 118 but also sometimes cause a potential barrier to occur immediately under the gate electrode 114, worsening the charge transfer efficiency of the transfer MOS transistor 102, which disadvantageously causes performance degradation of the CMOS image sensor itself.
Further, the angle A of the taper of the gate electrode 114 may vary in a wafer surface, resulting in another disadvantage that a general ion implantation apparatus of a wafer scan type cannot be used, but a special one of a type that performs scanning in a minute region has to be used.
On the other hand, with the method shown in FIG. 9, excessive thermal diffusion of impurities implanted into the P well 111 occurs not only in the transfer MOS transistor 102 but also in other transistors such as the select MOS transistor 105 and the reset MOS transistor 103. This arises a disadvantage that the space between paired source and drain regions of the above-mentioned other transistors are reduced, which is likely to cause punch-through. One method of avoiding such inconveniences could be increasing the gate length in size to preset the space between source and drain regions wide in the aforementioned other transistors. However, this method gives rise to another disadvantage that the density is reduced.
An object of the present invention is to provide a method of manufacturing a semiconductor device and a structure thereof, capable of providing an impurity-introduced region of a photodiode partly formed under a gate electrode without performing oblique-rotating implantation or excessive thermal diffusion.
According to a first aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) through (f). The step (a) is to prepare a substrate. The step (b) is to form a gate structure on a main surface of the substrate. The step (c) is to form a mask member having an opening over an end portion of the gate structure and over a specified region of the main surface adjacent to the end portion. The step (d) is to implant impurities from an almost vertical direction with respect to the main surface using the mask member as an implantation mask under conditions that the impurities can penetrate through a film thickness of the gate structure, thereby forming a first impurity-introduced region of a first conductivity type functioning as one electrode of a photodiode in the main surface under the end portion and in the specified region. The step (e) is to form a second impurity-introduced region of a second conductivity type functioning as the other electrode of the photodiode in the specified region. The step (f) is to form a third impurity-introduced region of the first conductivity type in the main surface to be opposite to the first impurity-introduced region with the gate structure interposed therebetween.
The first impurity-introduced region can be formed without performing oblique-rotating implantation or excessive thermal diffusion, allowing the impurity-introduced region to have less variations in the concentration distribution.
According to a second aspect of the invention, a semiconductor device includes a substrate, a photodiode formed in a main surface of the substrate and a transistor configured to transfer carriers generated in the photodiode. The photodiode has a first impurity-introduced region of a first conductivity type formed in the main surface, functioning as one electrode of the photodiode and a second impurity-introduced region of a second conductivity type formed in the main surface deeper than the first impurity-introduced region, functioning as the other electrode of the photodiode. The transistor includes a gate structure formed on the main surface, a first source/drain region formed with an end portion of the second impurity-introduced region extending into the main surface under the gate structure, and a second source/drain region being opposite to the first source/drain region with a channel forming region under the gate structure interposed therebetween. The first source/drain region has an impurity concentration distribution only in the depthwise direction of the substrate.
The first source/drain region has the impurity concentration distribution only in the depthwise direction of the substrate and not in a direction across the main surface of the substrate (i.e., the horizontal direction). This can prevent the occurrence of a potential barrier immediately under the gate structure as compared to a semiconductor device including a first source/drain region having the impurity concentration distribution in the horizontal direction, allowing the carrier transfer efficiency to be increased.